computer architecture problems

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2)Consider the pipelined implementation (without forwarding and/or stalling) of the MIPS microprocessor. (a) Explain how this pipelined implementation deals with I-type conditional branch instructions in the case the branch is not taken and in the case the branch is taken. (b) Explain why data dependency hazards may occur in this implementation. (c) List all possible instruction sequences that may exhibit data dependency hazards. (d) For each sequence in (c), give a software equivalent that does not suffer from the data dependency limitation. 3)Identify all of the data dependencies in the following code. Which dependencies are data hazards that will be resolved via forwarding? add $2, $5, $4 add $5, $2, $4 sw $5, 100($2) lw $4, 0($5) add $3, $2, $4 4) Assume a 5 stage pipelined MIPS processor with stages IF, ID, EX, MEM and WB. LOAD and STORE are the only instructions accessing memory. Branches are resolved at ID stage. (a) Give a code sequence that has data hazard which can be solved by forwarding. (b) Give a code sequence that has data hazard that cannot be solved by forwarding. Indicate stall cycles required. (c) Explain branch hazards. Why do branch hazards degrade the performance? 5)Consider the following MIPS code sequence. add $2, $2, $2 add $5, $5, $5 L: lw $8, 1000 ($5) sub $5, $2, $8 addi $2, $2, -4 beq $2, $0, L sw $5, 500 ($2) Assume that there is no forwarding unit (including register file forwarding) but instead there is a data hazard detection unit that introduces the stalls needed to avoid data hazards. Suppose the processor uses Assume Branch Not Taken strategy and branches are resolved in the ID stage. Illustrate the execution of the given code. 6)Using the same sequence of instructions as in Problem 5, now suppose the situation beq will be taken and branches are resolved in the ID stage (Processor uses Assume Branch Not Taken strategy). Show the execution of the given code around the loop, starting with the execution...

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